Hardware Engineering

Used an edge detector to generate clock signal

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Used a latch to remember signal's past state

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Wasted over two hours, but eventually finished the level

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Took over half an hour to finish a level

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Finished a level under 5 minutes thanks to practicing

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Spent an hour by completing a level

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Soldered 100 logic components

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Soldered 250 logic components

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Soldered 30 logic components, most of them badly

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Completed all levels on Digital Logic

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Completed a level using logic components only

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Used a microprocessor due to a shortage of storage capacity

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Used 100 words of executable code

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Used 250 words of executable code

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Used 30 words of executable words

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Completed a test sequence in the Sandbox mode

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Simulated throught 120 test steps

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Simulated through 30 test steps

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Simulated through 70 test steps

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Have 100 successful step simulations

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Have 50 successful step simulations

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Have 3:1 ratio of successful tests

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Have 1:3 ratio of successful tests

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Perform more successful than unsuccessful step simulations

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